The present invention relates to a method for manufacturing a semiconductor device, and is preferably applicable to, for example, a method for manufacturing a semiconductor device having a MISFET.
Over a semiconductor substrate, a gate electrode is formed via a gate insulation film. By ion implantation, or the like, source/drain regions are formed. As a result, a MISFET (Metal Insulator Semiconductor Field Effect Transistor: MIS field effect transistor or MIS transistor) can be formed.
Alternatively, over a semiconductor substrate, a dummy gate electrode is formed via a gate insulation film. By ion implantation, or the like, source/drain regions are formed. Then, the dummy gate electrode is replaced with a metal gate electrode. As a result, a MISFET can also be formed.
Japanese Unexamined Patent Application Publication No. 2014-127527 (Patent Document 1), Japanese Unexamined Patent Application Publication No 2013-26466 (Patent Document 2), and Japanese Unexamined Patent Application Publication No. 2012-99517 (Patent Document 3) each describe a technology of manufacturing a MISFET having a metal gate electrode by a gate-last process. Japanese Unexamined Patent Application Publication No. 2008-41939 (Patent Document 4) describes a technology regarding a silicon anisotropic etching method.